The objective in permanent or irreversible bonding of solid substrates is to produce a connection as strong and especially as permanent as possible, therefore a high bond force, between the two contact surfaces of the solid substrates. For this purpose, in the prior art there are various approaches and production methods, especially the welding of the surfaces at higher temperatures.
All types of materials, predominantly however metals and ceramics, are permanently bonded. One of the most important systems of permanent bonding is metal-metal systems. Cu—Cu systems have appeared increasingly in recent years. The development of 3D structures specifically requires mostly the joining of different functional layers. This joining is more and more often done by way of so-called TSVs (Through Silicon Vias). The contact-making of these TSVs with one another very often takes place by copper contact sites. At the instant of bonding very often there are full-value, serviceable structures, for example microchips, on one or more surfaces of the solid substrates. Since different materials with different coefficients of thermal expansion are used in microchips, increasing the temperature during bonding is not desirable. This can lead to thermal expansions and thus thermal stresses which can destroy parts of the microchip or its vicinity.
The known production methods and the approaches which have been followed to date often lead to results which cannot be reproduced or can be poorly reproduced and which can hardly be applied especially to altered conditions. In particular, production methods which are used at present often use high temperatures, especially >400° C., in order to ensure reproducible results.
Technical problems such as high energy consumption and a possible destruction of structures which are present on the substrates result from the high temperatures of in part far above 300° C. which have been necessary to date for a high bond force.
Other demands consist of the following:                (1) Front-end-of-line compatibility.        This is defined as the compatibility of the process during the production of the electrically active components. The bonding process must therefore be designed such that active components such as transistors, which are already present on the structure wafers, are neither adversely affected nor damaged during the processing. Compatibility criteria include mainly the purity of certain chemical elements (mainly in CMOS structures) and mechanical loadability, mainly by thermal stresses.        (2) Low contamination.        (3) No application of force, or application of force as low as possible.        (4) Temperature as low as possible, especially for materials with different coefficients of thermal expansion.        
The reduction of the bond force leads to more careful treatment of the structure wafer and thus to a reduction of the failure probability by direct mechanical loading, especially when the insulating layers between the metallic conductors are made from so-called “low-k” materials.
The welding of two surfaces works better, the flatter the surfaces, the less contamination on the surfaces, and the more perfect their surface structure. In reality it has to do with surfaces which are contaminated by water, organic substances, particles or the like which have a not negligible surface roughness and are very often more or less highly oxidized. The particles are removed in industry by various processes, generally in several modules which are independent of one another. The removal of oxides is certainly one of the most difficult challenges, since metal oxides are chemically rather stable. Even if all adhesive substances and chemically produced products are removed from the metal surface, there is still the rough surface as the last barrier to a perfect bond.
Current bonding methods are designed primarily for high pressures and temperatures. Mainly avoiding a high temperature is of essential importance for the welding of future semiconductor applications, since different materials with different coefficients of thermal expansion generate thermal stresses which cannot be ignored during heating and cooling processes. Furthermore, the diffusion of doping elements as the temperature rises is increasingly becoming a problem. The doped elements should not leave the intended three-dimensional region after the doping process. Otherwise the physical properties of the circuits would fundamentally change. In the best case this leads to a deterioration, in the worst and most probable case to unserviceability of the component. Mainly memories are susceptible to high temperatures due to their high transistor density and their high doping density. On the other hand, there are memories in which 3D technology is being increasingly used to raise the capacity and performance.
The problem in the existing prior art is to create a surface as flat as possible after decontamination of the surface. To some extent this is enabled by grinding processes. Grinding processes are however unable to perfectly planarize the surface. Another working step would be polishing. Here tools with special surfaces which further reduce the metal surface roughness are used. By a combination of grinding and polishing, roughnesses in the nanometer, often even in the subnanometer range, are produced. In most cases so-called CMP methods are used. It is a chemical-mechanical polishing process. Regardless of how long or how precisely grinding is done, a residual roughness which cannot be eliminated always results. This residual roughness upon contact of two surfaces always leads to formation of pores in the nanometer and subnanometer range.